Mentor Graphics FPGA Advantage V 7.2

FPGA Advantage is a complete Integrated Design Environment (IDE) targeting high-complexity FPGA device design. The FPGA Advantage IDE spans the RTL FPGA design flow featuring advanced design entry, verification, synthesis and implementation sub-flows. FPGA Advantage accelerates total product design with integration of FPGA IO design as well as bi-directional integration of the PCB design flow.

FPGA Advantage provides an integrated HDL flow for designing your FPGAs. FPGA Advantage enables design creation, simulation with debug and analysis, synthesis, management and documentation as a smooth flowing operation from one step to the next.

Each component of FPGA Advantage is a proven point tool, but the power comes from integrating these tools tightly together to create a unique HDL design methodology environment for VHDL and Verilog, on Windows® and UNIX®. HDL Designer Series™ serves as the cockpit for the design creation, reuse and management, and is the invocation bridge to the HDL simulation with ModelSim®, and Mentor Graphics synthesis.

The integration continues with Xilinx® CORE Generator™ and Xilinx ISE place and route (PAR) tools. FPGA Advantage encapsulates the CORE Generator and provides direct access to Xilinx IP cores. The symbol, the simulation model and the optimized EDIF netlist will be automatically placed into the hierarchical browser, enabling easy drag and drop of IP into the design.